Dynamic partial reconfiguration of logic controllers implemented in FPGAs

Grzegorz Bazydło; Remigiusz Wiśniewski

doi:10.1117/12.2249405

28 September 2016 Dynamic partial reconfiguration of logic controllers implemented in FPGAs

Grzegorz Bazydło, Remigiusz Wiśniewski

Proceedings Volume 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016; 100315B (2016) https://doi.org/10.1117/12.2249405
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, 2016, Wilga, Poland

Abstract

Technological progress in recent years benefits in digital circuits containing millions of logic gates with the capability for reprogramming and reconfiguring. On the one hand it provides the unprecedented computational power, but on the other hand the modelled systems are becoming increasingly complex, hierarchical and concurrent. Therefore, abstract modelling supported by the Computer Aided Design tools becomes a very important task. Even the higher consumption of the basic electronic components seems to be acceptable because chip manufacturing costs tend to fall over the time.

The paper presents a modelling approach for logic controllers with the use of Unified Modelling Language (UML). Thanks to the Model Driven Development approach, starting with a UML state machine model, through the construction of an intermediate Hierarchical Concurrent Finite State Machine model, a collection of Verilog files is created. The system description generated in hardware description language can be synthesized and implemented in reconfigurable devices, such as FPGAs. Modular specification of the prototyped controller permits for further dynamic partial reconfiguration of the prototyped system. The idea bases on the exchanging of the functionality of the already implemented controller without stopping of the FPGA device. It means, that a part (for example a single module) of the logic controller is replaced by other version (called context), while the rest of the system is still running. The method is illustrated by a practical example by an exemplary Home Area Network system.

Citation Download Citation

Grzegorz Bazydło and Remigiusz Wiśniewski "Dynamic partial reconfiguration of logic controllers implemented in FPGAs", Proc. SPIE 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, 100315B (28 September 2016); https://doi.org/10.1117/12.2249405

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