Optimization of complex high-dimensional layout configurations for IC physical designs using graph search, data analytics, and machine learning

Vito Dai; Edward Kah Ching Teoh; Ji Xu; Bharath Rangarajan

doi:10.1117/12.2262146

3 April 2017 Optimization of complex high-dimensional layout configurations for IC physical designs using graph search, data analytics, and machine learning

Vito Dai, Edward Kah Ching Teoh, Ji Xu, Bharath Rangarajan

Author Affiliations +

Proceedings Volume 10148, Design-Process-Technology Co-optimization for Manufacturability XI; 1014808 (2017) https://doi.org/10.1117/12.2262146
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States

Abstract

A typical new IC design has millions of layout configurations, not seen on previous product or test chip designs. Knowing the disposition of each and every configuration, problematic or not, is the key to optimizing design for yield. In this paper, we present a method to systematically characterize the configuration coverage of any layout. Coverage can be compared between designs, and configurations for which there is a lack of coverage can also be computed. When combined with simulation, metrology, and defect data for some configurations, graph search and machine learning algorithms can be applied to optimize designs for manufacturing yield.

Conference Presentation

Citation Download Citation

Vito Dai, Edward Kah Ching Teoh, Ji Xu, and Bharath Rangarajan "Optimization of complex high-dimensional layout configurations for IC physical designs using graph search, data analytics, and machine learning", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 1014808 (3 April 2017); https://doi.org/10.1117/12.2262146

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