A novel design-for-yield solution based on interconnect level layout improvements at 7nm technology node

Jaehwan Kim; Sangah Lee; Byungchul Shin; J. Jeon; Jin Kim; B. M. Kim; Jae-Hyun Kang; Seungweon Paek; Piyush Pathak; Frank E. Gennari; Philippe Hurat; Ya-Chieh Lai

doi:10.1117/12.2514896

4 April 2019 A novel design-for-yield solution based on interconnect level layout improvements at 7nm technology node

Jaehwan Kim, Sangah Lee, Byungchul Shin, J. Jeon, Jin Kim, B. M. Kim, Jae-Hyun Kang, Seungweon Paek, Piyush Pathak, Frank E. Gennari, Philippe Hurat, Ya-Chieh Lai

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Proceedings Volume 10962, Design-Process-Technology Co-optimization for Manufacturability XIII; 1096204 (2019) https://doi.org/10.1117/12.2514896
Event: SPIE Advanced Lithography, 2019, San Jose, California, United States

Abstract

Continuous scaling of CMOS process technology to 7nm (and below) has introduced new constraints and challenges in determining Design-for-Yield (DFY) solutions. In this work, traditional solutions such as improvements in redundancy and in compensating target designs for low process window margins are extended to meet the additional constraints of complex 7nm design rules. Experiments conducted on 7nm industrial designs demonstrate that the proposed solution achieves 9.1%-41% redundant-via-rate improvements while ensuring all 7nm design rule constraints are met.

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Jaehwan Kim, Sangah Lee, Byungchul Shin, J. Jeon, Jin Kim, B. M. Kim, Jae-Hyun Kang, Seungweon Paek, Piyush Pathak, Frank E. Gennari, Philippe Hurat, and Ya-Chieh Lai "A novel design-for-yield solution based on interconnect level layout improvements at 7nm technology node", Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096204 (4 April 2019); https://doi.org/10.1117/12.2514896

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