Edge placement error wafer mapping and investigation for improvement in advanced DRAM node

Kuan-Ming Chen; Wolfgang Henke; Ji-Hoon Jung; Ewa Kasperkiewicz; Anita Bouma; Rizvi Rahman; Gratiela Isai; Gwang-Gon Kim; Sotirios Tsiachris; Jae-Doug Yoo; Yuna Park; JaeYoung Park; Jonggeun Won; Nang-Lyeom Oh; Hsin-Yu Chen; WeiTai Lin; Chih-Hung Hsieh; Kuo-Feng Pao; Kyoyeon Cho; Abdalmohsen Elmalk; Sudharshanan Raghunathan; Taekwon Jee; Seung-Uk Jeong; Jeongwoo Jae; Sang-Woo Kim; Dongyoung Lee; Jungchan Kim; WonKwang Ma; Sang-Ho Lee; Chan-Ha Park

doi:10.1117/12.2584149

22 February 2021 Edge placement error wafer mapping and investigation for improvement in advanced DRAM node

Kuan-Ming Chen, Wolfgang Henke, Ji-Hoon Jung, Ewa Kasperkiewicz, Anita Bouma, Rizvi Rahman, Gratiela Isai, Gwang-Gon Kim, Sotirios Tsiachris, Jae-Doug Yoo, Yuna Park, JaeYoung Park, Jonggeun Won, Nang-Lyeom Oh, Hsin-Yu Chen, WeiTai Lin, Chih-Hung Hsieh, Kuo-Feng Pao, Kyoyeon Cho, Abdalmohsen Elmalk, Sudharshanan Raghunathan, Taekwon Jee, Seung-Uk Jeong, Jeongwoo Jae, Sang-Woo Kim, Dongyoung Lee, Jungchan Kim, WonKwang Ma, Sang-Ho Lee, Chan-Ha Park

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Proceedings Volume 11611, Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV; 116111V (2021) https://doi.org/10.1117/12.2584149
Event: SPIE Advanced Lithography, 2021, Online Only

Abstract

In this paper, budget characterization and wafer mapping of the Edge Placement Error (EPE) is studied to manage and improve pattern defects with a use case selected from SK Hynix’s most advanced DRAM 1x nm product. To quantify EPE, CD and overlay were measured at the multiple process steps and then combined for the EPE reconstruction. Massive metrology was used to capture extreme statistics and fingerprint across the wafer. An EPE budget breakdown was performed to identify main contributors and their variations. The end result shows EPEmax is mostly driven by local CD and overlay components while EPE variation is dominated by overlay and global CD components. Beyond EPE budget, a novel EPE wafer mapping methodology is introduced to visualize the temporal and spatial EPE performance which captures variation not seen from CD and overlay. This enables root-cause analysis of the pattern defects, and provides a foundation towards a better process monitoring solution. For EPE improvement, serial CD and overlay optimization simulation was performed to verify opportunities for reduction of the EPE and variation using the available ASML applications. The potential improvement for this use-case was confirmed to be 4.5% compared to baseline performance.

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Kuan-Ming Chen, Wolfgang Henke, Ji-Hoon Jung, Ewa Kasperkiewicz, Anita Bouma, Rizvi Rahman, Gratiela Isai, Gwang-Gon Kim, Sotirios Tsiachris, Jae-Doug Yoo, Yuna Park, JaeYoung Park, Jonggeun Won, Nang-Lyeom Oh, Hsin-Yu Chen, WeiTai Lin, Chih-Hung Hsieh, Kuo-Feng Pao, Kyoyeon Cho, Abdalmohsen Elmalk, Sudharshanan Raghunathan, Taekwon Jee, Seung-Uk Jeong, Jeongwoo Jae, Sang-Woo Kim, Dongyoung Lee, Jungchan Kim, WonKwang Ma, Sang-Ho Lee, and Chan-Ha Park "Edge placement error wafer mapping and investigation for improvement in advanced DRAM node", Proc. SPIE 11611, Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV, 116111V (22 February 2021); https://doi.org/10.1117/12.2584149

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