SDRAM timing design based on retina-like distributed CMOS sensor

Chao Fan; Fengmei Cao

doi:10.1117/12.2643863

20 December 2022 SDRAM timing design based on retina-like distributed CMOS sensor

Chao Fan, Fengmei Cao

Proceedings Volume 12314, Optoelectronic Devices and Integration XI; 123140V (2022) https://doi.org/10.1117/12.2643863
Event: SPIE/COS Photonics Asia, 2022, Online Only

Conference Poster

Abstract

In the research process of wireless transmission of retina-like distributed CMOS sensor, a design scheme of SDRAM controller based on FPGA is proposed to solve the problem of large amount of buffered data in real-time image acquisition system. A single-chip SDRAM is used as the data cache device, and the ping-pong read and write operation control scheme is implemented by switching Banks. Its purpose is to improve data transmission stability. And FIFO is used to solve the problem of clock domain crossing. The result of design is simulated by vivado. The waveform finally obtained shows that the design scheme can implement clock domain crossing and SDRAM operations of writing and reading. It can be used as an IP core in the SOC system.

Citation Download Citation

Chao Fan and Fengmei Cao "SDRAM timing design based on retina-like distributed CMOS sensor", Proc. SPIE 12314, Optoelectronic Devices and Integration XI, 123140V (20 December 2022); https://doi.org/10.1117/12.2643863

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