Design of DMS-RRIP replacement algorithm for L1-cache of RISC-V-based single-core embedded processor

Zining Ma; Honglan Jiang; Hongpeng Li; Yong Wu; Chenchen Deng; Leibo Liu

doi:10.1117/12.2685759

15 August 2023 Design of DMS-RRIP replacement algorithm for L1-cache of RISC-V-based single-core embedded processor

Zining Ma, Honglan Jiang, Hongpeng Li, Yong Wu, Chenchen Deng, Leibo Liu

Proceedings Volume 12719, Second International Conference on Electronic Information Technology (EIT 2023); 127194F (2023) https://doi.org/10.1117/12.2685759
Event: Second International Conference on Electronic Information Technology (EIT 2023), 2023, Wuhan, China

Abstract

As a new open-source reduced instruction set, RISC-V has received a large amount of attention. Because of its highly concise instruction set encoding and modular extended instruction sets, RISC-V instruction set has been widely used in the embedded system. As an indispensable part of the current embedded processor, cache directly affects the speed of the processor. In cache design, the cache replacement algorithm plays a key role, which is a necessary component affecting the hit rate of cache in. Aiming at the L1-Cache of RISC-V embedded processor, this paper proposes a cache replacement algorithm that dynamically adjusts the storage as per the memory access characteristics of the executing program. The simulation results show that the proposed replacement algorithm effectively improves the cache hit rate, and thus improves the overall performance of the processor.

Citation Download Citation

Zining Ma, Honglan Jiang, Hongpeng Li, Yong Wu, Chenchen Deng, and Leibo Liu "Design of DMS-RRIP replacement algorithm for L1-cache of RISC-V-based single-core embedded processor", Proc. SPIE 12719, Second International Conference on Electronic Information Technology (EIT 2023), 127194F (15 August 2023); https://doi.org/10.1117/12.2685759

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