Defect reduction strategies for process control and yield improvement

Douglas R. Liljegren

doi:10.1117/12.48960

1 March 1991 Defect reduction strategies for process control and yield improvement

Douglas R. Liljegren

Proceedings Volume 1392, Advanced Techniques for Integrated Circuit Processing; (1991) https://doi.org/10.1117/12.48960
Event: Processing Integration, 1990, Santa Clara, CA, United States

Abstract

The advent of automated defect inspection equipment has dramatically increased the quality and volume of visual defect data. The availability of this new information on a routine basis affords the opportunity to enhance the process quality improvement strategies currently in use however the volume of defect data and the variability of defect density makes use of this information difficult. In this flood of data the critical yield limiting defects are often difficult to discern. Process quality trouble shooting and control are difficult without proper analysis of defect data. A clear understanding of defect inspection technologies and defect data analysis requirements is essential to successful yield and reliability improvement. This paper examines the industry trends in the evolution and detection of defects on production wafers within a production facility. A model of average wafer defect density for each major device generation is presented. Implications to inspection technology and data analysis are discussed. Finally the requirements for detection and analysis of defects for current and future device technologies are discussed. BACKGROUND Wafer inspection for defects has evolved from manual visual and bright light inspections to fully automated inspection systems detecting sub-micron defects. Detection rates have increased from manual rates of a few centimeters per hour at variable capture rates on large defects to high speed detection of sub-micron defects with high stable capture rates. During this time wafer and chip sizes have increased

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Douglas R. Liljegren "Defect reduction strategies for process control and yield improvement", Proc. SPIE 1392, Advanced Techniques for Integrated Circuit Processing, (1 March 1991); https://doi.org/10.1117/12.48960

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KEYWORDS

Semiconducting wafers

Inspection

Yield improvement

Instrument modeling

Integrated circuits

Defect detection

Defect inspection

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