Gate oxide damage and evaluation techniques

Koichi Hashimoto; Daisuke Matsunaga; Masao Kanazawa

doi:10.1117/12.142913

16 April 1993 Gate oxide damage and evaluation techniques

Koichi Hashimoto, Daisuke Matsunaga, Masao Kanazawa

Proceedings Volume 1803, Advanced Techniques for Integrated Circuit Processing II; (1993) https://doi.org/10.1117/12.142913
Event: Microelectronic Processing '92, 1992, San Jose, CA, United States

Abstract

The quantities of the gate damage in an ECR plasma are evaluated as charge-up gate currents with the technique which employs Al gate MOS diodes and their sensitive flat band voltage shifts with current stress. A general model for charge-up damage is proposed. A charge-up I- V characteristic in the ECR plasma is estimated applying this technique, showing good agreement with that derived from the model. It is also deduced that the same I-V of the test device as the real device is essentially required for the correct evaluation. In a barrel reactor damage, antennas do not show the simple current collecting effect which has been expected.

Citation Download Citation

Koichi Hashimoto, Daisuke Matsunaga, and Masao Kanazawa "Gate oxide damage and evaluation techniques", Proc. SPIE 1803, Advanced Techniques for Integrated Circuit Processing II, (16 April 1993); https://doi.org/10.1117/12.142913

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