Scalable VLSI parallel pipelined architecture for discrete wavelet transform

Henry Y.H. Chuang; Ling Chen; Ching-Chung Li

doi:10.1117/12.150312

6 August 1993 Scalable VLSI parallel pipelined architecture for discrete wavelet transform

Henry Y.H. Chuang, Ling Chen, Ching-Chung Li

Proceedings Volume 2064, Machine Vision Applications, Architectures, and Systems Integration II; (1993) https://doi.org/10.1117/12.150312
Event: Optical Tools for Manufacturing and Advanced Automation, 1993, Boston, MA, United States

Abstract

The discrete wavelet transform (DWT) provides a new method for signal/image analysis where high frequency components are studied with finer time resolution and low frequency components with coarser time resolution. It decomposes a signal or an image into localized contributions for multiscale analysis. This paper presents a parallel pipelined array processor for 1-dimensional (1-D) DWT. Unlike other VLSI DWT processors which processes signal data sequentially in a pipeline, this array processor can process all data in a signal segment in parallel and successive segments in the same pipeline which computes the multiple levels (octaves) of DWT. The speedup is linearly proportional to the width of the array (or the size of a segment), and thus the architecture is scalable.

Citation Download Citation

Henry Y.H. Chuang, Ling Chen, and Ching-Chung Li "Scalable VLSI parallel pipelined architecture for discrete wavelet transform", Proc. SPIE 2064, Machine Vision Applications, Architectures, and Systems Integration II, (6 August 1993); https://doi.org/10.1117/12.150312

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