Paper
17 April 1995 New inner product algorithm of the two-dimensional DCT
Bela Feher
Author Affiliations +
Proceedings Volume 2419, Digital Video Compression: Algorithms and Technologies 1995; (1995) https://doi.org/10.1117/12.206392
Event: IS&T/SPIE's Symposium on Electronic Imaging: Science and Technology, 1995, San Jose, CA, United States
Abstract
The 2D discrete cosine transform (2D DCT) is one of the most effective methods in image data compression. In this paper an inner produce algorithm for the 8 X 8 2D DCT implementation is presented. The proposed direct 2D inner product algorithm exploits redundancies down to the bit level, and results in minimal hardware complexity. The basic algorithm separates the computation to 8 subtransform, according to the different cosine function values. Utilizing the odd-even property of the DCT, every transformed coefficients are expressed as a 4 point size inner product operation. The inner product processors are realized by an efficient distributed vector multiplication arrangement. All of the numerical parameters are built in into the inner product processors, so the arithmetic complexity is partly transformed to the internal topology of the units. The selected globally parallel, locally serial implementation style is features by basic serial processing elements and low communication cost. It is ideal for FPGA implementation, where the available chip area is a priori partitioned between logical and routing resources. The fully concurrent bit-serial pipeline architecture needs less than 1000 arithmetic primitives. Assuming 30 MHz bitclock rate in the Xilinx FPGA, the available throughput is 1 million 2D 8 X 8 DCT transform/sec.
© (1995) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bela Feher "New inner product algorithm of the two-dimensional DCT", Proc. SPIE 2419, Digital Video Compression: Algorithms and Technologies 1995, (17 April 1995); https://doi.org/10.1117/12.206392
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KEYWORDS
Field programmable gate arrays

Matrices

Logic

Signal processing

Clocks

Digital signal processing

Image compression

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