Improved figure-of-merit metric for CMOS transistor performance and its application to 0.25 um CMOS technologies

Amitava Chatterjee; Mark Rodder; Ih-Chin Chen

doi:10.1117/12.221123

15 September 1995 Improved figure-of-merit metric for CMOS transistor performance and its application to 0.25 um CMOS technologies

Amitava Chatterjee, Mark Rodder, Ih-Chin Chen

Author Affiliations +

Proceedings Volume 2636, Microelectronic Device and Multilevel Interconnection Technology; (1995) https://doi.org/10.1117/12.221123
Event: Microelectronic Manufacturing '95, 1995, Austin, TX, United States

Abstract

This paper presents an improved figure-of-merit (FOM) for CMOS performance which includes the effect of gate resistance. Performance degradation due to resistive polysilicon gates is modeled as an additional delay proportional to the RC product of a polysilicon line. The new FOM is verified from delay measurements on inverter chains fabricated using a 0.25 micrometers CMOS process. A furnace TiSi₂ process is used to underscore the effect of increased sheet resistance of narrow polysilicon lines. Excellent correlation between measured and predicted inverter chain delays is obtained over a variety of design, process and bias conditions. An expression for the gate sheet requirement is derived from the new FOM. Using this expression requirements on the gate sheet are calculated corresponding to a technology roadmap for performance and oxide thickness.

Citation Download Citation

Amitava Chatterjee, Mark Rodder, and Ih-Chin Chen "Improved figure-of-merit metric for CMOS transistor performance and its application to 0.25 um CMOS technologies", Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); https://doi.org/10.1117/12.221123

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