Modeling limits of multilevel interconnect technology

Bibiche Geuskens; Kenneth Rose

doi:10.1117/12.221146

15 September 1995 Modeling limits of multilevel interconnect technology

Bibiche Geuskens, Kenneth Rose

Proceedings Volume 2636, Microelectronic Device and Multilevel Interconnection Technology; (1995) https://doi.org/10.1117/12.221146
Event: Microelectronic Manufacturing '95, 1995, Austin, TX, United States

Abstract

Due to the continuing scaling down of minimum feature sizes, interconnect is becoming the limiting factor for on-chip performance. Alternative interconnect designs and new materials are needed to meet future performance expectations as predicted by the SIA Roadmap. We are developing models that can help designers in making initial evaluations about the possible performance impact of advanced interconnect designs and enhanced materials. In this paper, we apply these models to discuss the limitations of interconnect technology. In particular, we focus on the effects of interconnect materials on chip performance issues.

Citation Download Citation

Bibiche Geuskens and Kenneth Rose "Modeling limits of multilevel interconnect technology", Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); https://doi.org/10.1117/12.221146

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