Defect detection and control in an analog CMOS process

Franz Taucher; Ivor R. Evans

doi:10.1117/12.250844

12 September 1996 Defect detection and control in an analog CMOS process

Franz Taucher, Ivor R. Evans

Proceedings Volume 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II; (1996) https://doi.org/10.1117/12.250844
Event: Microelectronic Manufacturing 1996, 1996, Austin, TX, United States

Abstract

Over the last 12 months, Austria Mikro Systeme has installed an even more rigorous system of defect density measurement, monitoring and control in its facility at Unterpremstatten. To accomplish this, 2 test devices (Medusa 1 and 2) were designed which allow possible defects in all layers of the process to be located. These devices are 8 by 9 mm² in area and contain various structures to quantify the density of defects causing continuity, bridging and inter-layer isolation failure. The devices move through the waferfab receiving all process steps with the usual handling and operator procedures, from which it is clear, that the density of defects measured is representative of that of normal production material. The wafers are tested electrically using a Keithley S450, and data analysis is done with RS1 and EXCEL. By using yield models available from the literature, the correspondence in yield estimates made in this way and actual production yields were generally within 3%. Applying this technique allows the yield loss mechanisms to be isolated and then prioritized. The chipset identified several areas within the process which required special attention. These included implant optimization to reduce gate oxide damage, defect reduction in the metal-etch process, increased leakage currents caused by implant channeling and second poly etch-control to avoid 'bridging' around poly 1 periphery. Successful actions at these points have led to a significant improvement in wafer probe yields at Austria Mikro Systeme.

Citation Download Citation

Franz Taucher and Ivor R. Evans "Defect detection and control in an analog CMOS process", Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); https://doi.org/10.1117/12.250844

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