VLIW processor architecture adapted to FPAs

Laurent Petit; Jean-Didier Legat

doi:10.1117/12.324008

7 September 1998 VLIW processor architecture adapted to FPAs

Laurent Petit, Jean-Didier Legat

Proceedings Volume 3410, Advanced Focal Plane Arrays and Electronic Cameras II; (1998) https://doi.org/10.1117/12.324008
Event: SYBEN-Broadband European Networks and Electronic Image Capture and Publishing, 1998, Zurich, Switzerland

Abstract

A new processor architecture intended to be integrated with a CMOS image sensor is presented. This association allows to design an intelligent camera that can perform on-chip image processing tasks. The processor is based on a VLIW architecture with a reduced instruction bus, able to execute multiple instructions in a parallel without any loss of performance. In addition, no more instruction cache is required, decreasing in this way the hardware complexity.

Citation Download Citation

Laurent Petit and Jean-Didier Legat "VLIW processor architecture adapted to FPAs", Proc. SPIE 3410, Advanced Focal Plane Arrays and Electronic Cameras II, (7 September 1998); https://doi.org/10.1117/12.324008

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available