Combined level-to-level and within-level overlay control

Christopher P. Ausschnitt; Jaime D. Morillo; Roger J. Yerdon

doi:10.1117/12.473463

16 July 2002 Combined level-to-level and within-level overlay control

Christopher P. Ausschnitt, Jaime D. Morillo, Roger J. Yerdon

Proceedings Volume 4689, Metrology, Inspection, and Process Control for Microlithography XVI; (2002) https://doi.org/10.1117/12.473463
Event: SPIE's 27th Annual International Symposium on Microlithography, 2002, Santa Clara, California, United States

Abstract

Conventional overlay control minimizes the registration error between aligned level pairs. Post alignment corrections are applied to the adjustable parameters on the exposure tool. These can be grouped into grid terms relating to stepper stage control and field terms related to mask, stage and lens control. To minimize alignment time and alignment mark real estate on the wafer, common practice is to align at a fixed field location over a sufficient number of fields to represent the grid. A problem with conventional overlay control is that it places no constraint on the magnitude of field terms at first-level or any subsequent level; it requires only that they be matched between the alignment pairs. Incorporation of field-stitching overlay control within each level establishes the constraint that field terms remain consistent with the wafer stage stepping at each process level. A novel target layout and analysis method enables the simultaneous determination of both conventional overlay and neighboring-field error. Application of our method at first level and subsequent alignment levels precludes the random walk of field terms, thereby improving the consistency of field matching. The net result is an improvement in overlay control, particularly in cases where 'single-point' alignment or mixed tool set matching is required.

Citation Download Citation

Christopher P. Ausschnitt, Jaime D. Morillo, and Roger J. Yerdon "Combined level-to-level and within-level overlay control", Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); https://doi.org/10.1117/12.473463

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