Subresolution assist feature implementation for high-performance logic gate-level lithography

Allen H. Gabor; James A. Bruce; William Chu; Richard A. Ferguson; Carlos A. Fonseca; Ronald L. Gordon; Kenneth R. Jantzen; Mukesh Khare; Mark A. Lavin; Woo-Hyeong Lee; Lars W. Liebmann; Karl Paul Muller; Jed H. Rankin; Patrick Varekamp; Franz X. Zach

doi:10.1117/12.474591

30 July 2002 Subresolution assist feature implementation for high-performance logic gate-level lithography

Allen H. Gabor, James A. Bruce, William Chu, Richard A. Ferguson, Carlos A. Fonseca, Ronald L. Gordon, Kenneth R. Jantzen, Mukesh Khare, Mark A. Lavin, Woo-Hyeong Lee, Lars W. Liebmann, Karl Paul Muller, Jed H. Rankin, Patrick Varekamp, Franz X. Zach

Author Affiliations +

Proceedings Volume 4691, Optical Microlithography XV; (2002) https://doi.org/10.1117/12.474591
Event: SPIE's 27th Annual International Symposium on Microlithography, 2002, Santa Clara, California, United States

Abstract

This paper investigates the implementation of sub-resolution assist features (SRAFs) in high performance logic designs for the poly-gate conductor level. We will discuss the concepts used for SRAF rule generation, SRAF data preparation and what we term "binary" optical proximity correction (OPC) to prevent catastrophic line-width problems. Lithographic process window (PW) data obtained with SRAFs will be compared to PW data obtained without SRAF. SRAM cells are shown printed with annular illumination and SRAFs, for both the 130 nm and 100 nm logic nodes as defined by the International Technology Roadmap for Semiconductors (ITRS). This study includes a comparison of the experimental results of SRAMs printed from designs corrected with rule-based OPC to those printed from designs corrected with model-based OPC.

Citation Download Citation

Allen H. Gabor, James A. Bruce, William Chu, Richard A. Ferguson, Carlos A. Fonseca, Ronald L. Gordon, Kenneth R. Jantzen, Mukesh Khare, Mark A. Lavin, Woo-Hyeong Lee, Lars W. Liebmann, Karl Paul Muller, Jed H. Rankin, Patrick Varekamp, and Franz X. Zach "Subresolution assist feature implementation for high-performance logic gate-level lithography", Proc. SPIE 4691, Optical Microlithography XV, (30 July 2002); https://doi.org/10.1117/12.474591

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available