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This paper describes the validation of the methodology, the model and the impact of an optimized Lithography Defect Monitoring Strategy at two different semiconductor manufacturing factories. The lithography defect inspection optimization was implemented for the Gate Module at both factories running 0.13-0.15μm technologies on 200mm wafers, one running microprocessor and the other memory devices.
As minimum dimensions and process windows decrease in the lithography area, new technologies and technological advances with resists and resist systems are being implemented to meet the demands. Along with these new technological advances in the lithography area comes potentially unforeseen defect issues. The latest lithography processes involve new resists in extremely thin, uniform films, exposing the films under conditions of highly optimized focus and illumination, and finally removing the resist completely and cleanly. The lithography cell is defined as the cluster of process equipment that accomplishes the coating process (surface prep, resist spin, edge-bead removal and soft bake), the alignment and exposure,
and the developing process (post-exposure bake, develop, rinse) of the resist. Often the resist spinning process involves multiple materials such as BARC (bottom ARC) and / or TARC (top ARC) materials in addition to the resist itself. The introduction of these new materials with the multiple materials interfaces and the tightness of the process windows leads to an increased variety of defect mechanisms in the lithography area. Defect management in the lithography area has become critical to successful product introduction and yield ramp.
The semiconductor process itself contributes the largest number and variety of defects, and a significant portion of the total defects originate within the lithography cell. From a defect management perspective, the lithography cell has some unique characteristics. First, defects in the lithography process module have the widest range of sizes, from full-wafer to suboptical, and with the largest variety of characteristics. Some of these defects fall into the categories of coating problems, focus and exposure defects, developer defects, edge-bead removal problems, contamination and scratches usually defined as lithography macro defects as shown in Figure 1. Others fall into the category of lithography micro defects, Figure 2. They are characterized as having low topography such as stains, developer spots, satellites, are very small such as micro-bridging,
partial micro-bridging, micro-bubbles, CD variation and single isolated missing or deformed contacts or vias.
Lithography is the only area of the fab besides CMP in which defect excursions can be corrected by reworking the wafers. The opportunity to fix defect problems without scrapping wafers is best served by a defect inspection strategy that captures the full range of all relevant defect types with a proper balance between the costs of monitoring and inspection and the potential cost of yield loss. In the previous paper [1] it was shown that a combination of macro inspection and high numerical aperture (NA) brightfield imaging inspection technology is best suited for the application in the case of the idealized fab modeled. In this paper we will report on the successful efforts in implementing and validating the lithography defect monitoring strategy at two existing 200 mm factories running 0.15 μm and 0.13 μm design rules.
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