Ultralow-power ferroelectric memory for SoC

Sreedhar Natarajan; Atila Alvandpour

doi:10.1117/12.530438

30 March 2004 Ultralow-power ferroelectric memory for SoC

Proceedings Volume 5274, Microelectronics: Design, Technology, and Packaging; (2004) https://doi.org/10.1117/12.530438
Event: Microelectronics, MEMS, and Nanotechnology, 2003, Perth, Australia

Abstract

The endurance of a FRAM is 10¹⁴ cycles with better retention times (>10 years). FRAM's have fast read/write access, low standby current, scalable and capable of ultra-low voltage operation. FRAM's share architectural features such as addressing schemes and I/O circuitry with other types of random access memories (DRAMs), but they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. The FRAM is a great advantage for SoC and wireless and mobile products, since it supports non-volatility but also delivers a fast memory access. Today's 1T/1C FRAM have an access time of 30 nS, a cycle time of 35 nS at 1.2 V power supply in a standard CMOS process with 2 mask adders. The cell size of a FRAM is comparable to that of a planar DRAM and is 3 - 4x denser than SRAM. This paper outlines the circuit innovations in embedded ferroelectric memories, and will cover the architecture, reference circuits, sense amplifiers, reliability issues and references to other memory technologies.

Citation Download Citation

Sreedhar Natarajan and Atila Alvandpour "Ultralow-power ferroelectric memory for SoC", Proc. SPIE 5274, Microelectronics: Design, Technology, and Packaging, (30 March 2004); https://doi.org/10.1117/12.530438

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