Hybrid image sensor with multiple on-chip frame storage for ultrahigh-speed imaging

Vincent M. Douence; Yibin Bai; Hakan Durmus; Atul B. Joshi; Per-Olov Pettersson; Debashish Sahoo; Kris Kwiatkowski; Nicholas S.P. King; Christopher Morris; Mark D. Wilke

doi:10.1117/12.567552

17 March 2005 Hybrid image sensor with multiple on-chip frame storage for ultrahigh-speed imaging

Vincent M. Douence, Yibin Bai, Hakan Durmus, Atul B. Joshi, Per-Olov Pettersson, Debashish Sahoo, Kris Kwiatkowski, Nicholas S.P. King, Christopher Morris, Mark D. Wilke

Author Affiliations +

Proceedings Volume 5580, 26th International Congress on High-Speed Photography and Photonics; (2005) https://doi.org/10.1117/12.567552
Event: 26th International Congress on High-Speed Photography and Photonics, 2004, Alexandria, Virginia, United States

Abstract

A high-resolution hybrid visible imager, that is composed of a CMOS readout integrated circuit (ROIC) and a silicon photo-detector array, has been designed. The ROIC is fabricated with a standard 0.25 μm CMOS mixed-mode process with a back-illuminated silicon detector array that is produced at Rockwell Scientific Company (RSC) using RSC's HyViSI^TM process. The camera system is designed primarily to record images formed on a scintillator used in pulsed proton radiography experiments. In such experiments, the repetition rate of the proton beam can be as high as 2.8 MHz (358 ns). An imaging system with the desired 1440x1440 pixels resolution would result in an instantaneous readout rate in excess of 5.79 E12 samples/s. To address this issue we designed a pixel with three-frame in-pixel analog storage allowing for a deferred slower readout. The 26 μm pitch pixel imager is operated in a global shutter mode and features in-pixel correlated double sampling (CDS) for each of the three acquired frames. The CDS operation is necessary to overcome the kTC noise of the integrating node to achieve high dynamic range. A 65 fps continuous readout mode is also provided. The hybridized silicon array has close to 100% fill factor while anti-reflection (AR) coating maximizes its quantum efficiency at the scintillator emission wavelength (~415 nm). The ROIC is a 720x720, two-side buttable integrated circuit with on-chip 12-bit analog to digital converter (ADC) for digital readout. Timing and biasing are also generated on-chip, and special attention has been given to the power distribution of the pixel-array and snapshot signal buffers. This system-on-chip approach results in a compact and low power camera, an important feature to extend the number of imaged frames by synchronizing multiple cameras.

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Vincent M. Douence, Yibin Bai, Hakan Durmus, Atul B. Joshi, Per-Olov Pettersson, Debashish Sahoo, Kris Kwiatkowski, Nicholas S.P. King, Christopher Morris, and Mark D. Wilke "Hybrid image sensor with multiple on-chip frame storage for ultrahigh-speed imaging", Proc. SPIE 5580, 26th International Congress on High-Speed Photography and Photonics, (17 March 2005); https://doi.org/10.1117/12.567552

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