Design and Implementation of a Cellular-Logic VME Processor Module

Ruud Boekamp; Frans C. A. Groen; Frans A. Gerritsen; Ruud J. van Munster

doi:10.1117/12.952286

21 April 1986 Design and Implementation of a Cellular-Logic VME Processor Module

Ruud Boekamp, Frans C. A. Groen, Frans A. Gerritsen, Ruud J. van Munster

Proceedings Volume 0596, Architectures and Algorithms for Digital Image Processing III; (1986) https://doi.org/10.1117/12.952286
Event: 1985 International Technical Symposium/Europe, 1985, Cannes, France

Abstract

Cellular-logic (or morphological) operations such as erosion, dilation, contour extraction, propagation, skeletonization, local majority voting, and pepper-and-salt noise removal are essential tools in processing and measuring binary images. This paper describes the design and implementation of a Cellular Logic Processor module for use in VME-bus oriented image-processing systems. The Cellular-Logic Operators are implemented in a general way by table look-up, while using specialized hardware for address-generation, neighbourhood updating and bit-plane combination. The on-board memory accomodates four binary images (bitplanes) of 256 x 256 pixels each. The processor works at a 7.2 MHz pixel rate, performing a logical combination of two bitplanes, followed by a cellular-logic operation in a total of 9.2 ms.

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Ruud Boekamp, Frans C. A. Groen, Frans A. Gerritsen, and Ruud J. van Munster "Design and Implementation of a Cellular-Logic VME Processor Module", Proc. SPIE 0596, Architectures and Algorithms for Digital Image Processing III, (21 April 1986); https://doi.org/10.1117/12.952286

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