OPC and verification accuracy enhancement using the 2D wafer image for the low-k1 memory devices

Yong-Chan Ban; Dong-Yoon Lee; Ji-Suk Hong; Moon-Hyun Yoo; Jeong-Taek Kong

doi:10.1117/12.656280

15 March 2006 OPC and verification accuracy enhancement using the 2D wafer image for the low-k1 memory devices

Yong-Chan Ban, Dong-Yoon Lee, Ji-Suk Hong, Moon-Hyun Yoo, Jeong-Taek Kong

Proceedings Volume 6154, Optical Microlithography XIX; 61540J (2006) https://doi.org/10.1117/12.656280
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

The most important task in the OPC (optical proximity correction) process is to make a model database which can simulate optical behavior, while the characterization of resist development is still performed empirically. The previous approaches to lithography model generation heavily rely on 1 dimensional CD (critical dimension) measurements containing hundreds of features representing different sizes, shapes and pitches. Despite the huge amount of experiment data, there still can be a significant model error due to mismatching between measurement points and simulation points in 2 dimensional structures such as line ends, contact, and corners. Since the large number of data is required, it is quite natural that there require a huge computational effort to get the model. Our approach in this paper is based on the fitting model with 2D images, i.e., SEM image or a rigorous simulation image. It would not be an overstatement to say that a 2D wafer image is worth thousands of CD measurements. This approach is able to cover the symmetric as well as the non-symmetric patterns and prevents the threshold level from an inappropriate swing at the CTR (constant threshold resist) model. This paper aims to show how to extract the information of the wafer image, how to optimize the OPC modeling with quickness, and how to increase the modeling accuracy for the entire pattern. In addition, this paper shows the excellent agreement between the simulation image and the wafer image for the critical layout of the sub 70 nm technology node memory devices.

Citation Download Citation

Yong-Chan Ban, Dong-Yoon Lee, Ji-Suk Hong, Moon-Hyun Yoo, and Jeong-Taek Kong "OPC and verification accuracy enhancement using the 2D wafer image for the low-k1 memory devices", Proc. SPIE 6154, Optical Microlithography XIX, 61540J (15 March 2006); https://doi.org/10.1117/12.656280

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