An open source synthesisable model in VHDL of a 64-bit MIPS-based processor

Daniel R. Kelly; Braden J. Phillips; Said Al-Sarawi

doi:10.1117/12.695580

11 January 2007 An open source synthesisable model in VHDL of a 64-bit MIPS-based processor

Daniel R. Kelly, Braden J. Phillips, Said Al-Sarawi

Proceedings Volume 6414, Smart Structures, Devices, and Systems III; 641411 (2007) https://doi.org/10.1117/12.695580
Event: SPIE Smart Materials, Nano- and Micro-Smart Systems, 2006, Adelaide, Australia

Abstract

This report describes an open source VHDL description of a 64-bit MIPS-based processor. The pipeline can execute most instructions from the MIPS III instruction set architecture (ISA). The full pipeline is made available to digital VLSI engineers as a platform to test cell designs as a part of a complete computing system. The pipeline is an 8-stage RISC based on the MIPS R4000 series of processors, and includes common arithmetic operations on 32- and 64-bit operands, and full IEEE 754 floating point support. This report describes the architecture and components of the MIPS-based processor.

Citation Download Citation

Daniel R. Kelly, Braden J. Phillips, and Said Al-Sarawi "An open source synthesisable model in VHDL of a 64-bit MIPS-based processor", Proc. SPIE 6414, Smart Structures, Devices, and Systems III, 641411 (11 January 2007); https://doi.org/10.1117/12.695580

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