APF pitch-halving for 22nm logic cells using gridded design rules

Michael C. Smayling; Christopher Bencher; Hao D. Chen; Huixiong Dai; Michael P. Duane

doi:10.1117/12.772905

4 March 2008 APF pitch-halving for 22nm logic cells using gridded design rules

Michael C. Smayling, Christopher Bencher, Hao D. Chen, Huixiong Dai, Michael P. Duane

Proceedings Volume 6925, Design for Manufacturability through Design-Process Integration II; 69251E (2008) https://doi.org/10.1117/12.772905
Event: SPIE Advanced Lithography, 2008, San Jose, California, United States

Abstract

The 22nm logic technology node with dimensions of ~32nm will be the first node to require some form of pitch-halving. A unique combination of a Producer APF^(R)-based process sequence and GDR-based design style permits implementation of random logic functions with regular layout patterns. The APF (Advanced Patterning Film) pitch-halving approach is a classic Self-Aligned Double Patterning scheme (SADP) [1,2,3,4] which involves the creation of CVD dielectric spacers on an APF sacrificial template and using the spacers as a hardmask for line frequency doubling. The Tela Canva^TM implements Gridded Design Rules (GDR) using straight lines placed on a regular grid. Logic functions can be implemented using lines on a half-pitch with gaps at selected locations.

Citation Download Citation

Michael C. Smayling, Christopher Bencher, Hao D. Chen, Huixiong Dai, and Michael P. Duane "APF pitch-halving for 22nm logic cells using gridded design rules", Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69251E (4 March 2008); https://doi.org/10.1117/12.772905

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