Paper
30 December 2008 Self-aligned double-gate (DG) vertical nanoscale MOSFETs with reduced parasitic capacitance
Razali Ismail, Ismail Saad
Author Affiliations +
Proceedings Volume 7268, Smart Structures, Devices, and Systems IV; 72680U (2008) https://doi.org/10.1117/12.814129
Event: SPIE Smart Materials, Nano- and Micro-Smart Systems, 2008, Melbourne, Australia
Abstract
Enhanced symmetrical self-aligned double-gate (DG) vertical nMOSFET with low parasitic capacitance is presented. The process utilizes the oblique rotating ion implantation (ORI) method combined with fillet local oxidation (FILOX) technology (FILOX + ORI). Self-aligned region forms a sharp vertical channel profile that increased the number of electrons in the channel. These have improved drive-on current and drain-induced-barrier-lowering (DIBL) effect with a reduced off-state leakage current tremendously. The gate-to-drain capacitance is significantly reduced while having a small difference of gate-to-source capacitance compared to FILOX device. The drain overlap capacitance is a factor of 0.2 lower and the source overlap capacitance is a factor of 1.5 lower than standard vertical MOSFETs.
© (2008) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Razali Ismail and Ismail Saad "Self-aligned double-gate (DG) vertical nanoscale MOSFETs with reduced parasitic capacitance", Proc. SPIE 7268, Smart Structures, Devices, and Systems IV, 72680U (30 December 2008); https://doi.org/10.1117/12.814129
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Field effect transistors

Capacitance

Silicon

Electrons

Electrodes

Transistors

Oxides

Back to Top