Two-dimensional dose and focus-error measurement technology for exposure tool management in half-pitch 3x generation

Kazuhiko Fukazawa; Yuji Kudo; Yoshihiko Fujimori; Kiminori Yoshino; Yuichiro Yamazaki

doi:10.1117/12.813937

23 March 2009 Two-dimensional dose and focus-error measurement technology for exposure tool management in half-pitch 3x generation

Kazuhiko Fukazawa, Yuji Kudo, Yoshihiko Fujimori, Kiminori Yoshino, Yuichiro Yamazaki

Author Affiliations +

Proceedings Volume 7272, Metrology, Inspection, and Process Control for Microlithography XXIII; 72721I (2009) https://doi.org/10.1117/12.813937
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

As design rule of semiconductor device is shrinking, pattern profile management is becoming more critical, then high accuracy and high frequency is required for CD (Critical Dimension) and LER (Line Edge Roughness) measurements. We already presented the technology to inspect the pattern profile variations of entire wafer with high throughput [1] [2]. Using the technology, we can inspect CD&LER variations over the entire wafer quickly, but we could not separate the signal into CD and LER variations. This time, we measured the Stokes parameters, i.e., polarization status, in the reflected light from defected patterns. As the result, we could know the behavior of the polarization status changes by dose & focus defects, and we found the way to separate the signal into CD&LER variations, i.e. dose errors and focus errors, from S2 & S3 of Stokes parameters. We verified that we were able to calculate the values of CD&LER variations from S2 & S3 by the experiments. Furthermore, in order to solve the issue that many images are needed to calculate S2 & S3 values, we developed the new method to get CD&LER variations accurately in short time.

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Kazuhiko Fukazawa, Yuji Kudo, Yoshihiko Fujimori, Kiminori Yoshino, and Yuichiro Yamazaki "Two-dimensional dose and focus-error measurement technology for exposure tool management in half-pitch 3x generation", Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72721I (23 March 2009); https://doi.org/10.1117/12.813937

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KEYWORDS

Line edge roughness

Critical dimension metrology

Semiconducting wafers

Polarization

Inspection

Wafer testing

Scanning electron microscopy

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