Paper
1 April 2010 MAPPER: high-throughput maskless lithography
M. J. Wieland, G. de Boer, G. F. ten Berge, M. van Kervinck, R. Jager, J. J. M. Peijster, E. Slot, S. W. H. K. Steenbrink, T. F. Teepen, B. J. Kampherbeek
Author Affiliations +
Abstract
MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing with high speed optical data transport for switching the electron beams. In this way optical columns can be made with a throughput of 10-20 wafers per hour. By clustering several of these systems together high throughputs can be realized in a small footprint. This enables a highly cost-competitive alternative to double patterning and EUV alternatives[1]. In 2009 MAPPER shipped two systems one to TSMC and one to CEA-Leti. Both systems will be used to verify the applicability of MAPPER's technology for CMOS manufacturing. This paper presents a status update on the development of the MAPPER system over the past year. First an overview will be presented how to scale the current system to a 10 wph machine which can consequently be used in a cluster configuration to enable 100 wph throughputs. Then the results of today's (pre-) alpha systems with 300 mm wafer capability are presented from the machines at MAPPER, TSMC and CEA-Leti.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
M. J. Wieland, G. de Boer, G. F. ten Berge, M. van Kervinck, R. Jager, J. J. M. Peijster, E. Slot, S. W. H. K. Steenbrink, T. F. Teepen, and B. J. Kampherbeek "MAPPER: high-throughput maskless lithography", Proc. SPIE 7637, Alternative Lithographic Technologies II, 76370F (1 April 2010); https://doi.org/10.1117/12.849480
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Cited by 59 scholarly publications and 1 patent.
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KEYWORDS
Semiconducting wafers

Electron beams

Maskless lithography

Polymethylmethacrylate

Collimators

Lens design

Wafer-level optics

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