Line width roughness effects on device performance: the role of the gate width design

V. Constantoudis; E. Gogolides; G. P. Patsis

doi:10.1117/12.853317

2 April 2010 Line width roughness effects on device performance: the role of the gate width design

V. Constantoudis, E. Gogolides, G. P. Patsis

Proceedings Volume 7641, Design for Manufacturability through Design-Process Integration IV; 764116 (2010) https://doi.org/10.1117/12.853317
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

The role of the gate width in the effects of Line Width Roughness (LWR) on transistor performance is investigated. Two mathematical results regarding the statistical nature of LWR are presented and discussed. The implications of these results on the effects of LWR on transistor performance are investigated through a 2D modeling approach. It is found that, for fixed LWR induced by manufacturing processes, transistors designed with large gate widths seem to mitigate the degradation effects of LWR on transistor performance.

Citation Download Citation

V. Constantoudis, E. Gogolides, and G. P. Patsis "Line width roughness effects on device performance: the role of the gate width design", Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 764116 (2 April 2010); https://doi.org/10.1117/12.853317

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