An analog logarithmic number system subtractor for edge detection in logarithmic CMOS image sensors

D. R. Desai; F. H. Hassan; R. J. Veillette; J. E. Carletta

doi:10.1117/12.872461

16 February 2011 An analog logarithmic number system subtractor for edge detection in logarithmic CMOS image sensors

D. R. Desai, F. H. Hassan, R. J. Veillette, J. E. Carletta

Proceedings Volume 7875, Sensors, Cameras, and Systems for Industrial, Scientific, and Consumer Applications XII; 78750C (2011) https://doi.org/10.1117/12.872461
Event: IS&T/SPIE Electronic Imaging, 2011, San Francisco Airport, California, United States

Abstract

This paper describes the design of analog circuitry to implement logarithmic number system (LNS) subtraction. Such circuitry, if incorporated in the readout circuitry of a logarithmic CMOS image sensor, would allow for the on-chip calculation of spatial derivatives, while operating directly on logarithmically-scaled pixels. The circuit was implemented for a 1.2μm CMOS process. The maximum relative error at the output of the LNS subtractor for pixel currents that correspond to an illumination range of more than four decades is 4.26%.

Citation Download Citation

D. R. Desai, F. H. Hassan, R. J. Veillette, and J. E. Carletta "An analog logarithmic number system subtractor for edge detection in logarithmic CMOS image sensors", Proc. SPIE 7875, Sensors, Cameras, and Systems for Industrial, Scientific, and Consumer Applications XII, 78750C (16 February 2011); https://doi.org/10.1117/12.872461

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