Wafer noise models for defect inspection

Timothy F. Crimmins

doi:10.1117/12.879477

20 April 2011 Wafer noise models for defect inspection

Timothy F. Crimmins

Proceedings Volume 7971, Metrology, Inspection, and Process Control for Microlithography XXV; 79710E (2011) https://doi.org/10.1117/12.879477
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

The ability to simulate patterned wafer inspection microscopy is important to guide equipment development, with defect signal-to-noise being the key output metric. With the ongoing introduction of aggressively low k1 lithography, the contribution of wafer noise is becoming one of the dominant noise elements. Quantitative noise models which accurately represent wafer noise are required. The present work develops structural models for line edge roughness and surface roughness. Aerial image FDTD simulations are performed on the model structures and the relationships between the model parameters and defect signal-to-wafer-noise are explored, with conclusions being drawn regarding the wafer inspection sensitivity process window.

Citation Download Citation

Timothy F. Crimmins "Wafer noise models for defect inspection", Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 79710E (20 April 2011); https://doi.org/10.1117/12.879477

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