Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device

Yu-Jin Pyo; Soo-Han Choi; Chul-Hong Park; Sang-Hoon Lee; Moon-Hyun Yoo; Gyu-Tae Kim

doi:10.1117/12.869978

4 April 2011 Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device

Yu-Jin Pyo, Soo-Han Choi, Chul-Hong Park, Sang-Hoon Lee, Moon-Hyun Yoo, Gyu-Tae Kim

Author Affiliations +

Proceedings Volume 7974, Design for Manufacturability through Design-Process Integration V; 797413 (2011) https://doi.org/10.1117/12.869978
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

Double-patterning technology (DPT) has been a primary lithography candidate of the sub-30nm technology node. The major concern of DPT is the critical dimension (CD) skew and overlay error between 1st and 2nd patterning, which cause the degradation of the electrical performance in terms of timing delay. In this paper, we newly develop a systematic method to determine the DPT scheme and the proper process specification using a statistical approach in perspective of the pattering and electrical performance. Applying the method to the bit-line layer of the sub-30nm DRAM device, we determine the DPT scheme (i.e. either litho-etch-litho-etch (LELE) or self-aligned double pattering (SADP) to avoid the patterning hotspots. In addition, analyzing the statistical simulation result, we provide the process specification and exposing sequence of two masks to avoid the electrical degradation.

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Yu-Jin Pyo, Soo-Han Choi, Chul-Hong Park, Sang-Hoon Lee, Moon-Hyun Yoo, and Gyu-Tae Kim "Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device", Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797413 (4 April 2011); https://doi.org/10.1117/12.869978

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