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It is well known that VLSI circuits must be designed to sustain the variations in process, voltage, temperature, etc. As a result, standard cell libraries (collections of the basic circuit components) are usually designed with large margin (also known as “timing slack”). However, in circuit manufacturing, only part of the margin will be utilized. The knowledge of the rest of the margin (over-designed timing slack), armed with models that link between timing domain and shape domain, can help to reduce the complexity of mask patterns and manufacturing cost. This paper proposed a novel methodology to simplify mask patterns in optical proximity correction (OPC) by using extra margin in timing (over-designed timing slack). This methodology can be applied after a conventional OPC, and is compatible with the current application-specific integrated circuit (ASIC) design flow. This iterative method is applied to each occurrence of over-designed timing slack. The actual value of timing slack can be estimated from post-OPC simulation. A timing cost function is developed in this work to map timing slack in timing domain to mask patterns in shape domain. This enables us to adjust mask patterns selectively based on the outcome of the cost function. All related mask patterns with over-designed timing slack will be annotated and simplified using our proposed mask simplification algorithm, which is in fact to merge the nearby edge fragments on the mask patterns. Simulations are conducted on a standard cell library and a full chip design to validate this proposed approach. When compared to existing OPC methods without mask simplification in the literature, our approach achieved a 51% reduction in mask fragment count, and this directly leads to a large saving in lithography manufacturing cost. The result also shows that timing closure is ensured, though part of the timing slack has been sacrificed.
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