Energy-efficient STDP-based learning circuits with memristor synapses

Xinyu Wu; Vishal Saxena; Kristy A. Campbell

doi:10.1117/12.2053359

22 May 2014 Energy-efficient STDP-based learning circuits with memristor synapses

Xinyu Wu, Vishal Saxena, Kristy A. Campbell

Proceedings Volume 9119, Machine Intelligence and Bio-inspired Computation: Theory and Applications VIII; 911906 (2014) https://doi.org/10.1117/12.2053359
Event: SPIE Sensing Technology + Applications, 2014, Baltimore, MD, United States

Abstract

It is now accepted that the traditional von Neumann architecture, with processor and memory separation, is ill suited to process parallel data streams which a mammalian brain can efficiently handle. Moreover, researchers now envision computing architectures which enable cognitive processing of massive amounts of data by identifying spatio-temporal relationships in real-time and solving complex pattern recognition problems. Memristor cross-point arrays, integrated with standard CMOS technology, are expected to result in massively parallel and low-power Neuromorphic computing architectures. Recently, significant progress has been made in spiking neural networks (SNN) which emulate data processing in the cortical brain. These architectures comprise of a dense network of neurons and the synapses formed between the axons and dendrites. Further, unsupervised or supervised competitive learning schemes are being investigated for global training of the network. In contrast to a software implementation, hardware realization of these networks requires massive circuit overhead for addressing and individually updating network weights. Instead, we employ bio-inspired learning rules such as the spike-timing-dependent plasticity (STDP) to efficiently update the network weights locally. To realize SNNs on a chip, we propose to use densely integrating mixed-signal integrate-andfire neurons (IFNs) and cross-point arrays of memristors in back-end-of-the-line (BEOL) of CMOS chips. Novel IFN circuits have been designed to drive memristive synapses in parallel while maintaining overall power efficiency (<1 pJ/spike/synapse), even at spike rate greater than 10 MHz. We present circuit design details and simulation results of the IFN with memristor synapses, its response to incoming spike trains and STDP learning characterization.

Citation Download Citation

Xinyu Wu, Vishal Saxena, and Kristy A. Campbell "Energy-efficient STDP-based learning circuits with memristor synapses", Proc. SPIE 9119, Machine Intelligence and Bio-inspired Computation: Theory and Applications VIII, 911906 (22 May 2014); https://doi.org/10.1117/12.2053359

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available