Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

Miloš A. Popović; Mark T. Wade; Jason S. Orcutt; Jeffrey M. Shainline; Chen Sun; Michael Georgas; Benjamin Moss; Rajesh Kumar; Luca Alloatti; Fabio Pavanello; Yu-Hsin Chen; Kareem Nammari; Jelena Notaros; Amir Atabaki; Jonathan Leu; Vladimir Stojanović; Rajeev J. Ram

doi:10.1117/12.2084604

3 April 2015 Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

Miloš A. Popović, Mark T. Wade, Jason S. Orcutt, Jeffrey M. Shainline, Chen Sun, Michael Georgas, Benjamin Moss, Rajesh Kumar, Luca Alloatti, Fabio Pavanello, Yu-Hsin Chen, Kareem Nammari, Jelena Notaros, Amir Atabaki, Jonathan Leu, Vladimir Stojanović, Rajeev J. Ram

Author Affiliations +

Proceedings Volume 9367, Silicon Photonics X; 93670M (2015) https://doi.org/10.1117/12.2084604
Event: SPIE OPTO, 2015, San Francisco, California, United States

Abstract

We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a “More-than- Moore” technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

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Miloš A. Popović, Mark T. Wade, Jason S. Orcutt, Jeffrey M. Shainline, Chen Sun, Michael Georgas, Benjamin Moss, Rajesh Kumar, Luca Alloatti, Fabio Pavanello, Yu-Hsin Chen, Kareem Nammari, Jelena Notaros, Amir Atabaki, Jonathan Leu, Vladimir Stojanović, and Rajeev J. Ram "Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems", Proc. SPIE 9367, Silicon Photonics X, 93670M (3 April 2015); https://doi.org/10.1117/12.2084604

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