Paper
19 March 2015 Effect of wafer geometry on lithography chucking processes
Kevin T. Turner, Jaydeep K. Sinha
Author Affiliations +
Abstract
Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kevin T. Turner and Jaydeep K. Sinha "Effect of wafer geometry on lithography chucking processes", Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 94240L (19 March 2015); https://doi.org/10.1117/12.2085693
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Cited by 1 scholarly publication.
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KEYWORDS
Semiconducting wafers

Lithography

Optical lithography

Mechanics

Neodymium

Spatial frequencies

Etching

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