Advanced overlay analysis through design based metrology

Sunkeun Ji; Gyun Yoo; Gyoyeon Jo; Hyunwoo Kang; Minwoo Park; Jungchan Kim; Chanha Park; Hyunjo Yang; Donggyu Yim; Kotaro Maruyama; Byungjun Park; Masahiro Yamamoto

doi:10.1117/12.2085464

19 March 2015 Advanced overlay analysis through design based metrology

Sunkeun Ji, Gyun Yoo, Gyoyeon Jo, Hyunwoo Kang, Minwoo Park, Jungchan Kim, Chanha Park, Hyunjo Yang, Donggyu Yim, Kotaro Maruyama, Byungjun Park, Masahiro Yamamoto

Author Affiliations +

Proceedings Volume 9424, Metrology, Inspection, and Process Control for Microlithography XXIX; 942415 (2015) https://doi.org/10.1117/12.2085464
Event: SPIE Advanced Lithography, 2015, San Jose, California, United States

Abstract

As design rule shrink, overlay has been critical factor for semiconductor manufacturing. However, the overlay error which is determined by a conventional measurement with an overlay mark based on IBO and DBO often does not represent the physical placement error in the cell area. The mismatch may arise from the size or pitch difference between the overlay mark and the cell pattern. Pattern distortion caused by etching or CMP also can be a source of the mismatch. In 2014, we have demonstrated that method of overlay measurement in the cell area by using DBM (Design Based Metrology) tool has more accurate overlay value than conventional method by using an overlay mark. We have verified the reproducibility by measuring repeatable patterns in the cell area, and also demonstrated the reliability by comparing with CD-SEM data. We have focused overlay mismatching between overlay mark and cell area until now, further more we have concerned with the cell area having different pattern density and etch loading. There appears a phenomenon which has different overlay values on the cells with diverse patterning environment. In this paper, the overlay error was investigated from cell edge to center. For this experiment, we have verified several critical layers in DRAM by using improved(Better resolution and speed) DBM tool, NGR3520.

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Sunkeun Ji, Gyun Yoo, Gyoyeon Jo, Hyunwoo Kang, Minwoo Park, Jungchan Kim, Chanha Park, Hyunjo Yang, Donggyu Yim, Kotaro Maruyama, Byungjun Park, and Masahiro Yamamoto "Advanced overlay analysis through design based metrology", Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 942415 (19 March 2015); https://doi.org/10.1117/12.2085464

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KEYWORDS

Overlay metrology

Semiconducting wafers

Metrology

Data analysis

Etching

Double patterning technology

Optical lithography

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