Paper
18 December 2014 SOI layout decomposition for double patterning lithography on high-performance computer platforms
Author Affiliations +
Proceedings Volume 9440, International Conference on Micro- and Nano-Electronics 2014; 94400X (2014) https://doi.org/10.1117/12.2180809
Event: The International Conference on Micro- and Nano-Electronics 2014, 2014, Zvenigorod, Russian Federation
Abstract
In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on 45 nm Nangate Open Cell Library including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Vladimir Verstov, Lyudmila Zinchenko, and Vladimir Makarchuk "SOI layout decomposition for double patterning lithography on high-performance computer platforms", Proc. SPIE 9440, International Conference on Micro- and Nano-Electronics 2014, 94400X (18 December 2014); https://doi.org/10.1117/12.2180809
Lens.org Logo
CITATIONS
Cited by 2 scholarly publications.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Double patterning technology

Metals

Lithography

Silicon

Very large scale integration

Computing systems

Optical lithography

Back to Top