Analyzing block placement errors in SADP patterning

Shinji Kobayashi; Soichiro Okada; Satoru Shimura; Kathleen Nafus; Carlos Fonseca; Marc Demand; Serge Biesemans; Janko Versluijs; Monique Ercken; Philippe Foubert; Shinobu Miyazaki

doi:10.1117/12.2218597

21 March 2016 Analyzing block placement errors in SADP patterning

Shinji Kobayashi, Soichiro Okada, Satoru Shimura, Kathleen Nafus, Carlos Fonseca, Marc Demand, Serge Biesemans, Janko Versluijs, Monique Ercken, Philippe Foubert, Shinobu Miyazaki

Author Affiliations +

Proceedings Volume 9779, Advances in Patterning Materials and Processes XXXIII; 97791T (2016) https://doi.org/10.1117/12.2218597
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States

Abstract

We discuss edge placement errors (EPE) for multi-patterning of Mx critical layers using ArF lithography. Specific focus is placed on the block formation part of the process. While plenty of literature characterization data exist on spacer formation, only limited published data is available on block processes. We analyze the accuracy of placing blocks relative to narrow spacers. Many publications calculate EPE assuming Gaussian distributions for key process variations contributing to EPE. For practical reasons, each contributor is measured on dedicated test structures. In this work, we complement such analysis and directly measure the EPE in product. We perform high density sampling of blocks using CDSEM images and analyze all feature edges of interest. We find that block placement errors can be very different depending on their local design context. Specifically we report on 2 block populations (further called block A and B) which have a 4x different standard deviation. We attribute this to differences in local topography (spacer shape) and interaction with the plasma-etch process design. Block A (on top of the ‘core space’ S1) has excellent EPE uniformity of ~1 nm while block B (on top of ‘gap space’ S2) has degraded EPE control of ~4 nm. Finally, we suggest that the SOC etch process is at the origin on positioning blocks accurately on slim spacers, helping the manufacturability of spacer-based patterning techniques, and helping its extension toward the 5nm node.

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Shinji Kobayashi, Soichiro Okada, Satoru Shimura, Kathleen Nafus, Carlos Fonseca, Marc Demand, Serge Biesemans, Janko Versluijs, Monique Ercken, Philippe Foubert, and Shinobu Miyazaki "Analyzing block placement errors in SADP patterning", Proc. SPIE 9779, Advances in Patterning Materials and Processes XXXIII, 97791T (21 March 2016); https://doi.org/10.1117/12.2218597

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KEYWORDS

Semiconducting wafers

System on a chip

Etching

Optical lithography

Device simulation

Plasma etching

Scanning electron microscopy

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