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Patterning contact-hole mask for Flash/DRAM is probably one of the most challenging tasks for design rule below 50nm due to the extreme low-k1 printing conditions common in the memory designs. When combined with optical proximity corrections (OPC) to the mask, using optimized illumination has become a viable part of the production lithography process for 65nm node. At k1<0.31, both resolution and imaging contrast can become severely limited by some of the current imaging tools with NA<0.85 and using standard illumination sources. Hyper-NA immersion lithography increases the process latitude and is therefore expected to become more indispensable for manufacturing under extreme low-k1 conditions for sub-50nm design rule. In this work, we describe our process optimization approach for patterning Flash/DRAM contact-hole patterns with 130nm, 120nm, and smaller minimum pitch design rules. Here we use 6% attPSM mask for simulation and actual exposure in ASML XT 1400i (NA=0.93) and 1700i (NA=1.2) respectively. We begin with the illumination source optimization using full vector high-NA calculation (VHNA) with production resist stack and all manufacturability requirements for the source shaping diffractive optical element (DOE) are accounted for during the source optimization. Using the optimized source, IMLTM technology based scattering bars (SB) placement together with model based OPC (MOPC) are applied to the original contact-hole design. In-focus printing and process latitude simulations are used to gauge the performance and manufacturability of the final optimized process, which includes the optimized mask, optimized source and required imaging settings. Our results show that for the 130nm pitch Flash contact-hole patterns, on ASML XT 1400i at NA=0.93, both optimized illumination source and immersion lithography are necessary in order to achieve manufacturability. The worst-case depth of focus (DOF) before SB and MOPC is 100-130nm at 6% EL, without common process window (PW) and with MOPC, the worst-case DOF is >200nm at 6% EL. The latter is in excellent agreement with the wafer results from ASML XT 1400i, and the predicated CDs match well with the measured at isolated, medium and dense pitch contact-holes to within 5nm. For the 120nm pitch Flash contact patterns, ASML XT 1700i at NA=1.2 must be used, together with optimized illumination source, to achieve the same or better process latitude (worst-case DOF at 6% EL), and for the Flash pattern used, further enhancements of >20% in DOF @ 6% EL using Y linear polarization can be achieved, before SB and MOPC. With preliminary SB and MOPC, the worst-case DOF @ 6% EL is increased from 100nm to 150nm and with common PW for all critical CDs, from isolated to dense contact-holes. Two examples of customized polarizations are considered in the above simulations to demonstrate the effects of polarizations on imaging and process latitude for pattern specific contact-holes. The pros and cons of the current patterning solution are discussed and compared with alternatives.
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