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Proceedings Article

A high aspect ratio Si-fin FinFET fabricated with 193nm scanner photolithography and thermal oxide hard mask etching techniques

[+] Author Affiliations
Wen-Shiang Liao

United Microelectronics Corp. (Taiwan)

Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 615612 (March 14, 2006); doi:10.1117/12.659648
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From Conference Volume 6156

  • Design and Process Integration for Microelectronic Manufacturing IV
  • Alfred K. K. Wong; Vivek K. Singh
  • San Jose, CA | February 19, 2006

abstract

A vertical double gate (FinFET) devices with a high Si-fin aspect ratio of height/width (H/W) = 87nm/11nm have been successfully fabricated on SOI wafers. Firstly, a 50nm-thick capping oxide layer was thermally grown upon the SOI crystalline silicon layer. Secondly, both 105nm-thick BARC and 265nm-thick photoresist were coated and a 193nm scanner lithography tool was used for the Si-fin layout patterning under high ASML exposure energy. Then, a deep sub-micron plasma etcher was used for an aggressive photoresist and BARC trimming down processing and the Si-fin capping oxide layer was subsequently plasma etched in another etching chamber without breaking the plasma etcher's loadlock vacuum. Continuously, the photoresist and BARC were removed with a plasma ashing and a RCA cleaning. Also, the patterned Si-fin capping oxide can be further trimmed down with an additional DHF cleaning and the remained ~22nm-thick capping oxide was still thick enough to act as a robust hard mask for the subsequent Si-fin plasma etching. Finally, an ultra thin Si-fin width 11nm and Si-fin height of 87nm can be successfully fabricated through the last silcon plasma etching.

© (2006) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Citation

Wen-Shiang Liao
"A high aspect ratio Si-fin FinFET fabricated with 193nm scanner photolithography and thermal oxide hard mask etching techniques", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 615612 (March 14, 2006); doi:10.1117/12.659648; http://dx.doi.org/10.1117/12.659648


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