Etch challenges for 1xnm NAND flash

Myung Kyu Ahn; Woo June Kwon; Chan Sun Hyun; Jin Woong Kim

doi:10.1117/12.920313

16 March 2012 Etch challenges for 1xnm NAND flash

Myung Kyu Ahn, Woo June Kwon, Chan Sun Hyun, Jin Woong Kim

Proceedings Volume 8328, Advanced Etch Technology for Nanopatterning; 83280F (2012) https://doi.org/10.1117/12.920313
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

In recent years, NAND flash technology node has shrunk below to 1x nm patterning with significant progresses of double patterning technology (DPT) and spacer patterning technology (SPT). Plasma etching processes involved in the fabrication of advanced NAND flash device become increasingly challenging. As critical dimensions decrease, controlling of micro-loading and pattern wiggling such as line edge roughness (LER) and line width roughness (LWR) has become key issues. In order to define the fine pattern, plasma etch process regime has been changed to lower pressure and to higher plasma density below sub 40 nm. However, below 20 nm, it seems that control of pressure and plasma density is not enough. In an effort to overcome these huddles, pulsing plasma etch technology has been evaluated for 1x nm node. By using pulsing plasma we have obtained the improvement of etch selectivity and reduction of poly hard mask loss. In this study, we have found that pulse applied etching as well as film stack optimization is remarkably effective to reduce micro-loading and pattern wiggling.

Citation Download Citation

Myung Kyu Ahn, Woo June Kwon, Chan Sun Hyun, and Jin Woong Kim "Etch challenges for 1xnm NAND flash", Proc. SPIE 8328, Advanced Etch Technology for Nanopatterning, 83280F (16 March 2012); https://doi.org/10.1117/12.920313

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