An optimal adder-based hardware architecture for the DCT/SA-DCT

Andrew Kinane; Valentin Muresan; Noel O'Connor

doi:10.1117/12.633190

24 June 2005 An optimal adder-based hardware architecture for the DCT/SA-DCT

Andrew Kinane, Valentin Muresan, Noel O'Connor

Proceedings Volume 5960, Visual Communications and Image Processing 2005; 596045 (2005) https://doi.org/10.1117/12.633190
Event: Visual Communications and Image Processing 2005, 2005, Beijing, China

Abstract

The explosive growth of the mobile multimedia industry has accentuated the need for efficient VLSI implementations of the associated computationally demanding signal processing algorithms. This need becomes greater as end-users demand increasingly enhanced features and more advanced underpinning video analysis. One such feature is object-based video processing as supported by MPEG-4 core profile, which allows content-based interactivity. MPEG-4 has many computationally demanding underlying algorithms, an example of which is the Shape Adaptive Discrete Cosine Transform (SA-DCT). The dynamic nature of the SA-DCT processing steps pose significant VLSI implementation challenges and many of the previously proposed approaches use area and power consumptive multipliers. Most also ignore the subtleties of the packing steps and manipulation of the shape information. We propose a new multiplier-less serial datapath based solely on adders and multiplexers to improve area and power. The adder cost is minimised by employing resource re-use methods. The number of (physical) adders used has been derived using a common sub-expression elimination algorithm. Additional energy efficiency is factored into the design by employing guarded evaluation and local clock gating. Our design implements the SA-DCT packing with minimal switching using efficient addressing logic with a transpose memory RAM. The entire design has been synthesized using TSMC 0.09μm TCBN90LP technology yielding a gate count of 12028 for the datapath and its control logic.

Citation Download Citation

Andrew Kinane, Valentin Muresan, and Noel O'Connor "An optimal adder-based hardware architecture for the DCT/SA-DCT", Proc. SPIE 5960, Visual Communications and Image Processing 2005, 596045 (24 June 2005); https://doi.org/10.1117/12.633190

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available