EUV lithography for 30nm half pitch and beyond: exploring resolution, sensitivity, and LWR tradeoffs

E. Steve Putna; Todd R. Younkin; Manish Chandhok; Kent Frasure

doi:10.1117/12.814191

1 April 2009 EUV lithography for 30nm half pitch and beyond: exploring resolution, sensitivity, and LWR tradeoffs

E. Steve Putna, Todd R. Younkin, Manish Chandhok, Kent Frasure

Proceedings Volume 7273, Advances in Resist Materials and Processing Technology XXVI; 72731L (2009) https://doi.org/10.1117/12.814191
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a leading technology option for realizing the 32nm half-pitch node and beyond. Readiness of EUV materials is currently one high risk area according to assessments made at the 2008 EUVL Symposium. The main development issue regarding EUV resist has been how to simultaneously achieve high sensitivity, high resolution, and low line width roughness (LWR). This paper describes the strategy and current status of EUV resist development at Intel Corporation. Data is presented utilizing Intel's Micro-Exposure Tool (MET) examining the feasibility of establishing a resist process that simultaneously exhibits ≤30nm half-pitch (HP) L/S resolution at ≤10mJ/cm² with ≤4nm LWR.

Citation Download Citation

E. Steve Putna, Todd R. Younkin, Manish Chandhok, and Kent Frasure "EUV lithography for 30nm half pitch and beyond: exploring resolution, sensitivity, and LWR tradeoffs", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 72731L (1 April 2009); https://doi.org/10.1117/12.814191

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