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Proceedings Article

Advances and challenges in dual-tone development process optimization

[+] Author Affiliations
Carlos Fonseca, Mark Somervell, Steven Scheer, Wallace Printz

Tokyo Electron America, Inc. (USA)

Kathleen Nafus, Shinichi Hatakeyama, Yuhei Kuwahara, Takafumi Niwa

Tokyo Electron Kyushu, Ltd. (Japan)

Sophie Bernard, Roel Gronheid

IMEC (Belgium)

Proc. SPIE 7274, Optical Microlithography XXII, 72740I (March 16, 2009); doi:10.1117/12.814289
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From Conference Volume 7274

  • Optical Microlithography XXII
  • Harry J. Levinson; Mircea V. Dusa
  • San Jose, California, USA | February 22, 2009


The ever-shrinking circuit device dimensions challenge lithographers to explore viable patterning for the 32 nm halfpitch node and beyond. Significant improvements in immersion lithography have allowed extension of optical lithography down to 45 nm node and likely into early 32 nm node development. In the absence of single-exposure patterning solutions, double patterning techniques are likely to extend immersion lithography for 32 nm node manufacturing. While several double patterning techniques have been proposed as viable manufacturing solutions, cost, along with technical capability, will dictate which candidate is adopted by the industry. Dual-tone development (DTD) has been proposed as a potential cost-effective double patterning technique.1 Dual-tone development was reported as early as in the late 1990's by Asano.2 The basic principle of dual-tone imaging involves processing exposed resist latent images in both positive tone (aqueous base) and negative tone (organic solvent) developers. Conceptually, DTD has attractive cost benefits since it enables pitch doubling without the need for multiple etch steps of patterned resist layers. While the concept for DTD technique is simple to understand, there are many challenges that must be overcome and understood in order to make it a manufacturing solution. This work presents recent advances and challenges associated with DTD. Experimental results in conjunction with simulations are used to understand and advance learning for DTD. Experimental results suggest that clever processing on the wafer track can be used to enable DTD beyond 45 nm half-pitch dimensions for a given resist process. Recent experimental results also show that DTD is capable of printing <0.25 k1-factor features with an ArF immersion scanner. Simulation results showing co-optimization of process variables, illumination conditions, and mask properties are presented.

© (2009) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Carlos Fonseca ; Mark Somervell ; Steven Scheer ; Wallace Printz ; Kathleen Nafus, et al.
"Advances and challenges in dual-tone development process optimization", Proc. SPIE 7274, Optical Microlithography XXII, 72740I (March 16, 2009); doi:10.1117/12.814289; http://dx.doi.org/10.1117/12.814289

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