A thick CESL stressed ultra-small (Lg=40-nm) SiGe-channel MOSFET fabricated with 193-nm scanner lithography and TEOS hard mask etching

Wen-Shiang Liao; Tung-Hung Chen; Hsin-Hung Lin; Wen-Tung Chang; Tommy Shih; Huan-Chiu Tsen; Lee Chung

doi:10.1117/12.708935

27 March 2007 A thick CESL stressed ultra-small (Lg=40-nm) SiGe-channel MOSFET fabricated with 193-nm scanner lithography and TEOS hard mask etching

Wen-Shiang Liao, Tung-Hung Chen, Hsin-Hung Lin, Wen-Tung Chang, Tommy Shih, Huan-Chiu Tsen, Lee Chung

Author Affiliations +

Proceedings Volume 6520, Optical Microlithography XX; 65204P (2007) https://doi.org/10.1117/12.708935
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

A 100Å-thick SiGe (22.5%) channel MOSFET with gate length down to 40nm has been successfully integrated with 14Å nitrided gate oxide as well as a 1200Å high-compressive PECVD ILD-SiNx stressing layer as the contact etching stop layer (CESL) that enhances the PMOS electron mobility with +33% current gain. To achieve a poly-Si gate length target of 400Å (40nm), a 193nm scanner lithography and an aggressive oxide hard mask etching techniques were used. First, a 500Å-thick TEOS hard mask layer was deposited upon the 1500Å-thick poly-Si gate electrode. Second, both 1050Å-thick bottom anti-reflective coating (BARC) and 2650Å-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the gate layout patterning with nominal logic 90nm exposure energy. Then, a deep sub-micron plasma etcher was used for an aggressive P/R and BARC trimming down processing and the TEOS hard mask was subsequently plasma etched in another etching chamber without breaking the plasma etcher’s vacuum. Continuously, the P/R and BARC were removed with a plasma ashing and RCA cleaning. Moreover, the patterned Si-fin capping oxide can be further trimmed down with a diluted HF_(aq) solution (DHF) while rendering the RCA cleaning process and the remained TEOS hard mask is still thick enough for the subsequent poly-Si gate main etching. Finally, an ultra narrow poly-Si gate length of 40nm with promising PMOS drive current enhancement can be formed through a second poly-Si etching, which is above the underneath SiGe (22.5%) conduction channel as well as its upper 14Å-thick nitrided gate oxide.

Citation Download Citation

Wen-Shiang Liao, Tung-Hung Chen, Hsin-Hung Lin, Wen-Tung Chang, Tommy Shih, Huan-Chiu Tsen, and Lee Chung "A thick CESL stressed ultra-small (Lg=40-nm) SiGe-channel MOSFET fabricated with 193-nm scanner lithography and TEOS hard mask etching", Proc. SPIE 6520, Optical Microlithography XX, 65204P (27 March 2007); https://doi.org/10.1117/12.708935

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
6 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Etching

Photomasks

Oxides

Lithography

Plasma

Scanners

Field effect transistors

Show All Keywords

Keywords/Phrases

Search In:

Publication Years