Paper
23 September 2009 AIMS mask qualification for 32nm node
Author Affiliations +
Abstract
Moving forward to 32nm node and below optical lithography using 193nm is faced with complex requirements to be solved. Mask makers are forced to address both Double Patterning Techniques and Computational Lithography approaches such as Source Mask Optimizations and Inverse Lithography. Additionally, lithography at low k1 values increases the challenges for mask repair as well as for repair verification and review by AIMSTM. Higher CD repeatability, more flexibility in the illumination settings as well as significantly improved image performance must be added when developing the next generation mask qualification equipment. This paper reports latest measurement results verifying the appropriateness of the latest member of AIMSTM measurement tools - the AIMSTM 32-193i. We analyze CD repeatability measurements on lines and spaces pattern. The influence of the improved optical performance and newly introduced interferometer stage will be verified. This paper highlights both the new Double Patterning functionality emulating double patterning processes and the influence of its critical parameters such as overlay errors and resist impact. Beneficial advanced illumination schemes emulating scanner illumination document the AIMSTM 32-193i to meet mask maker community's requirements for the 32nm node.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Rigo Richter, Thomas Thaler, Holger Seitz, Ulrich Stroessner, and Thomas Scheruebl "AIMS mask qualification for 32nm node", Proc. SPIE 7488, Photomask Technology 2009, 74882R (23 September 2009); https://doi.org/10.1117/12.830083
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Photomasks

Double patterning technology

Scanners

Source mask optimization

Lithography

Computational lithography

Lithographic illumination

RELATED CONTENT

Extension of practical k1 limit in EUV lithography
Proceedings of SPIE (March 18 2016)
450mm lithography status for high volume manufacturing
Proceedings of SPIE (March 24 2017)
Double patterning study with inverse lithography
Proceedings of SPIE (March 26 2008)
Optical lithography applied to 20-nm CMOS Logic and SRAM
Proceedings of SPIE (March 22 2011)

Back to Top