This paper presents a backside-to-frontside alignment technique for the backside processing of Si wafers. Integrated MEMS components like BiCMOS-embedded RF-MEMS switches require accurate (1-2μm) alignment. We demonstrate an alignment technique providing overlay values of less than 500 nm by using a backside alignment layer. The approach is enabled by a new non-contact wafer pre-alignment system of the Nikon Scanner S207D allowing precise loading (<5μm) of the wafer onto the exposure stage. Before starting the back-side MEMS process, the misalignment between frontside devices and backside alignment layer has to be measured. The alignment errors are applied as lithography overlay corrections to the backside MEMS process. For the specific application of deep Si etching (Bosch process), moreover, one has to consider the etch profile angle deviation across the wafer (tilting), which turned out in our experiments to amount up to 8 μm. During initial experiments with a Nikon i-line stepper NSR-2205 i- 11D the overlay has been corrected by the stepper offset parameters. These parameters have been obtained by summing up both the wafer and intra-field scaling errors caused by deep Si etching and backside-to-frontside alignment errors. Misalignments and tilting errors were all measured with a MueTec MT 3000 IR optical metrology system using overlay marks. The developed alignment technique is applied to BiCMOS-embedded MEMS devices, i.e. mm-wave RF switches and a viscosity sensor chip based on the IHP's high-speed SiGe technology. It turned out to be very promising for backside processed MEMS components with critical alignment requirements.© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.