Full Content is available to subscribers

Subscribe/Learn More  >
Proceedings Article

Implementation of scalable video coding deblocking filter from high-level SystemC description

[+] Author Affiliations
Pedro P. Carballo, Omar Espino, Romén Neris, Pedro Hernández-Fernández, Tomasz M. Szydzik, Antonio Núñez

Univ. de Las Palmas de Gran Canaria (Spain)

Proc. SPIE 8764, VLSI Circuits and Systems VI, 876408 (May 28, 2013); doi:10.1117/12.2016885
Text Size: A A A
From Conference Volume 8764

  • VLSI Circuits and Systems VI
  • Teresa Riesgo; Massimo Conti
  • Grenoble, France | April 24, 2013


This paper describes key concepts in the design and implementation of a deblocking filter (DF) for a H.264/SVC video decoder. The DF supports QCIF and CIF video formats with temporal and spatial scalability. The design flow starts from a SystemC functional model and has been refined using high‐level synthesis methodology to RTL microarchitecture. The process is guided with performance measurements (latency, cycle time, power, resource utilization) with the objective of assuring the quality of results of the final system. The functional model of the DF is created in an incremental way from the AVC DF model using OpenSVC source code as reference. The design flow continues with the logic synthesis and the implementation on the FPGA using various strategies. The final implementation is chosen among the implementations that meet the timing constraints. The DF is capable to run at 100 MHz, and macroblocks are processed in 6,500 clock cycles for a throughput of 130 fps for QCIF format and 37 fps for CIF format. The proposed architecture for the complete H.264/SVC decoder is composed of an OMAP 3530 SOC (ARM Cortex‐A8 GPP + DSP) and the FPGA Virtex‐5 acting as a coprocessor for DF implementation. The DF is connected to the OMAP SOC using the GPMC interface. A validation platform has been developed using the embedded PowerPC processor in the FPGA, composing a SoC that integrates the frame generation and visualization in a TFT screen. The FPGA implements both the DF core and a GPMC slave core. Both cores are connected to the PowerPC440 embedded processor using LocalLink interfaces. The FPGA also contains a local memory capable of storing information necessary to filter a complete frame and to store a decoded picture frame. The complete system is implemented in a Virtex5 FX70T device. © (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Pedro P. Carballo ; Omar Espino ; Romén Neris ; Pedro Hernández-Fernández ; Tomasz M. Szydzik, et al.
" Implementation of scalable video coding deblocking filter from high-level SystemC description ", Proc. SPIE 8764, VLSI Circuits and Systems VI, 876408 (May 28, 2013); doi:10.1117/12.2016885; http://dx.doi.org/10.1117/12.2016885

Access This Article
Sign In to Access Full Content
Please Wait... Processing your request... Please Wait.
Sign in or Create a personal account to Buy this article ($15 for members, $18 for non-members).



Citing articles are presented as examples only. In non-demo SCM6 implementation, integration with CrossRef’s "Cited By" API will populate this tab (http://www.crossref.org/citedby.html).

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging & repositioning the boxes below.

Related Book Chapters

Topic Collections


Buy this article ($18 for members, $25 for non-members).
Sign In