Wafer-level 3D integration with 5 micron interconnect pitch for infrared imaging applications

Matthew Lueck; John Lannon Jr.; Chris Gregory; Dean Malta; A. Huffman; Dorota S. Temple

doi:10.1117/12.2058166

21 May 2014 Wafer-level 3D integration with 5 micron interconnect pitch for infrared imaging applications

Matthew Lueck, John Lannon Jr., Chris Gregory, Dean Malta, A. Huffman, Dorota S. Temple

Proceedings Volume 9100, Image Sensing Technologies: Materials, Devices, Systems, and Applications; 910009 (2014) https://doi.org/10.1117/12.2058166
Event: SPIE Sensing Technology + Applications, 2014, Baltimore, MD, United States

Abstract

The use of 3D integration technology in focal plane array imaging devices has been shown to increase imaging capability while simultaneously decreasing device area and power consumption, as compared to analogous 2D designs. A key enabling technology for 3D integration is the use of high density metal-metal bonding to form pixel-level interconnects between device layers. In this paper, we review recent progress in high density, sub-10 μm pitch interconnect bonding for 3D integration of imaging systems. Specifically, we will present results from successful demonstrations of the use of Cu microbumps for the interconnection of 5 μm pitch 640×512 and 1280×1024 arrays. Operability of the arrays of bonded interconnects in two-layer silicon die stacks was greater than 99.99% with good electrical isolation between bonds.

Citation Download Citation

Matthew Lueck, John Lannon Jr., Chris Gregory, Dean Malta, A. Huffman, and Dorota S. Temple "Wafer-level 3D integration with 5 micron interconnect pitch for infrared imaging applications", Proc. SPIE 9100, Image Sensing Technologies: Materials, Devices, Systems, and Applications, 910009 (21 May 2014); https://doi.org/10.1117/12.2058166

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