Automatic DFM methodology for bit line pattern dummy

Mohamed Bahr

doi:10.1117/12.2185545

18 March 2015 Automatic DFM methodology for bit line pattern dummy

Mohamed Bahr

Proceedings Volume 9427, Design-Process-Technology Co-optimization for Manufacturability IX; 942715 (2015) https://doi.org/10.1117/12.2185545
Event: SPIE Advanced Lithography, 2015, San Jose, California, United States

Abstract

This paper presents an automated DFM solution to generate Bit Line Pattern Dummy (BLPD) for memory chips. Dummy shapes are aligned with memory functional bits lines to ensure uniform and reliable memory device. This paper will present a smarter approach that uses an analysis based technique for adding the dummy fill shapes that have different types according to the space available. Experimental results based on layout of a memory test chip.

Citation Download Citation

Mohamed Bahr "Automatic DFM methodology for bit line pattern dummy", Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 942715 (18 March 2015); https://doi.org/10.1117/12.2185545

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