HVM capabilities of CPE run-to-run overlay control

Lokesh Subramany; Woong Jae Chung; Karsten Gutjahr; Miguel Garcia-Medina; Christian Sparka; Lipkong Yap; Onur Demirer; Ramkumar Karur-Shanmugam; Brent Riggs; Vidya Ramanathan; John C. Robinson; Bill Pierson

doi:10.1117/12.2190852

19 March 2015 HVM capabilities of CPE run-to-run overlay control

Lokesh Subramany, Woong Jae Chung, Karsten Gutjahr, Miguel Garcia-Medina, Christian Sparka, Lipkong Yap, Onur Demirer, Ramkumar Karur-Shanmugam, Brent Riggs, Vidya Ramanathan, John C. Robinson, Bill Pierson

Author Affiliations +

Proceedings Volume 9424, Metrology, Inspection, and Process Control for Microlithography XXIX; 94241V (2015) https://doi.org/10.1117/12.2190852
Event: SPIE Advanced Lithography, 2015, San Jose, California, United States

Abstract

With the introduction of N2x and N1x process nodes, leading-edge factories are facing challenging demands of shrinking design margins. Previously un-corrected high-order signatures, and un-compensated temporal changes of high-order signatures, carry an important potential for improvement of on-product overlay (OPO). Until recently, static corrections per exposure (CPE), applied separately from the main APC correction, have been the industry’s standard for critical layers [1], [2]. This static correction is setup once per device and layer and then updated periodically or when a machine change point generates a new overlay signature. This is a non-ideal setup for two reasons. First, any drift or sudden shift in tool signature between two CPE update periods can cause worse OPO and a higher rework rate, or, even worse, lead to yield loss at end of line. Second, these corrections are made from full map measurements that can be in excess of 1,000 measurements per wafer [3].

Advanced overlay control algorithms utilizing Run-to-Run (R2R) CPE can be used to reduce the overlay signatures on product in High Volume Manufacturing (HVM) environments. In this paper, we demonstrate the results of a R2R CPE control scheme in HVM. The authors show an improvement up to 20% OPO Mean+3Sigma values on several critical immersion layers at the 28nm and 14 nm technology nodes, and a reduction of out-of-spec residual points per wafer (validated on full map). These results are attained by closely tracking process tool signature changes by means of APC, and with an affordable metrology load which is significantly smaller than full wafer measurements.

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Lokesh Subramany, Woong Jae Chung, Karsten Gutjahr, Miguel Garcia-Medina, Christian Sparka, Lipkong Yap, Onur Demirer, Ramkumar Karur-Shanmugam, Brent Riggs, Vidya Ramanathan, John C. Robinson, and Bill Pierson "HVM capabilities of CPE run-to-run overlay control", Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 94241V (19 March 2015); https://doi.org/10.1117/12.2190852

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